1. Technical Field of the Invention
The present invention relates to a gate voltage regulation system for the programming and/or soft programming phase of non volatile memory cells. More particularly, the invention relates to a gate voltage regulation system for the programming and/or soft programming phase of non volatile memory cells, for example of the flash type, with low circuit area occupation.
2. Description of Related Art
As it is well known in this specific technical field, in modern semiconductor-integrated non volatile memory devices, for example in flash EEPROM memories, the need to apply very “precise” voltages to memory cells in the writing step is increasingly felt. This is generally valid both for writing cells having a grounded bulk terminal, essentially with Vbulk=0, and for negative Vbulk writing.
Writing operations for a Flash memory are essentially of two types:                real programming, in order to change the logic status of a cell from erased to programmed; and        soft programming, which is a low efficiency kind of programming required to control more precisely the threshold shift of a given cell.        
Usually, a soft programming is necessary after an erasing in order to recover all those bits whose threshold near to zero could cause false reading problems in a NOR memory architecture.
The circuits involved in both the programming and the soft programming operation are essentially the same, differing only in that the voltages required in the soft programming phase are lower than the voltages of the programming phase. More particularly, the following rules quoted in Table 1 are generally valid:
TABLE 1ProgrammingSoft ProgrammingVgateRampVstart-p, Vfinal-p,Vstart-p, Vfinal-p,ΔTpulse-pΔTpulse-pVdrainConst.VdVdVbulkConst.0 or negative0 or negativeVsourceConst.00
Essentially, the programming phase is performed by applying a ramp voltage on the memory cell gate terminal, thus ensuring (if performed with a quite precise ramp slope) the desired threshold shift in the desired time and with a constant current. By indicating the voltage values at the ramp beginning and end with the references Vstart and Vfinal and the ramp duration with Tprogram, a constant current programming is obtained, as shown in FIG. 1.
The ramp can be generally formed in two ways:                analogue; which is obtained by means of a linear ramp; and        through pulses; which is obtained by means of several short pulses in order to interpolate the linear feature.        
The problems linked to the creation of a pulse ramp will now be considered. Such a voltage ramp must be linear with values Vstart, Vfinal, Tpulse=Tprogram being as independent as possible from operating conditions, such as for example:                Vsupply, memory device supply voltage;        operating temperature; and        capacitive load change        
It is not simple at all to manufacture a circuitry which succeeds, with low area occupation, in ensuring a constant ramp when the above-mentioned operating conditions vary. Moreover, once the regulation system to be used is defined and fixed, it does not mean that it equally suits both the programming and the soft programming phase.
The potential limits of a single regulation system will be examined first. The problems linked to the use of a single regulation system for both phases will be briefly analyzed.
Programming: in this case the voltage ramp, starting from low values being almost equal to the supply voltage for 3V-operating memories is brought to values near to technology-supportable values, for example ˜10V. In this case it is necessary to form a ramp as near as possible to the ideal ramp, but without having a series regulator, since the voltage difference ΔV required at the regulator series transistor terminals would lead to an upstream voltage being dangerously near, if not even higher than the borderline voltage provided by the technology.
Referring to what has been described above, FIG. 2A, showing a threshold voltage distribution of memory array cells, can be observed. The programmed cell distribution is indicated with D2. The cell distribution after erasing is indicated with D1. Cells to be recovered after the erasing operation are in grey.
Similarly, FIG. 2B shows a threshold voltage distribution of the cells of a memory array wherein cells being over-recovered after the erasing operation are represented in percentage in grey, in the case of a high efficiency charge pump.
Generally, it is preferable to connect the charge pump output, responsible for the voltage ramp creation, directly to the gate node, by using an ON/OFF regulation. In this case problems are those linked to the pump efficiency. In fact, as shown in FIG. 3, in the ramp lower part, at low voltages, a high pump efficiency occurs, but this could lead to serious regulation problems intended as a ripple which cannot be easily controlled, and thus to a distorted ramp trend very far from being ideal. If the pump efficiency is to be decreased, serious problems could arise in the ramp upper part, where the pump would have difficulty to follow the ideal ramp, as shown in FIG. 4.
Soft Programming: in this case the problem is even more serious. In fact the charge pump operates at even lower voltage values, generally lower than supply voltages for a 3V-powered memory device. Therefore, the ripple management becomes in this case very demanding.
The technical problem underlying the present invention is to provide a gate voltage regulation system, particularly for the programming and soft programming phase of non volatile memory cells, having such structural and functional characteristics as to improve the voltage regulator answer fidelity at low voltages, overcoming the limits of present prior art solutions.